In re Ogiue

RICH, Judge. This appeal is from the decision of the Patent and Trademark Office (PTO) Board of Appeals affirming the final rejection of claims 10-19 (see Appendix), all the claims remaining in appellant’s — 1383 — application, serial No. 870,946, filed October 8, 1969,1 entitled “Manufacture of Semiconductor Device.” We affirm. PACTS The Invention In the manufacture of integrated semiconductor circuits, the art prefers to isolate electrically the several regions on the surface of the semiconductor chip from one another by means of reverse-biased PN junctions. According to appellant, this was done before his invention by epitaxially depositing a mono-crystalline layer of one conductivity type on a monocrystalline substrate of a second conductivity type, and then selectively diffusing an impurity through the epitaxial layer down to the surface of the substrate, so as to define an annular or grid-like region of the first conductivity type on the substrate of the second conductivity type. The disadvantage of this method is that the decrease of impurity concentration as the diffused layer deepens prevents adequate isolation unless the diffusion treatment is effected at high temperatures or for long periods of time, which causes auto-doping of the epitaxial layer by the impurities in the substrate. Appellant claims to have invented an improved electrical isolation technique, embodied in a semiconductor device fabricated in accordance with his invention. His specification says: The gist of this invention resides in that a plurality of monocrystalline semiconductor layers and a polycrystalline semiconductor layer integrally and contiguously provided between said monocrystalline semiconductor layers are formed on a surface of a material serving as a substrate, and that said monocrystalline layers (these layers are used to define circuit elements or as means for providing a desired circuit function) are electrically isolated from each other by said substrate and said polycrystalline layer. To this end, a region of an opposite conductivity type to that of said mono-crystalline layers is included in said polycrystalline layer. The formation of this opposite conductivity type region is effected by virtue of the nature of an impurity that is diffused at a high speed into the polycrystalline semiconductor layer (that is, the fact that it has a high diffusion coefficient). Fig. 3 of the application illustrates in part the manufacture of appellant’s device: Silicon dioxide (Si02) layers 21 are deposited through a mask onto a P-type mono-crystalline substrate 1. The substrate is then placed in a reaction furnace, through which flows a silicon halide (SiCh) gas containing an N-type impurity, so that a semiconductor silicon layer is epitaxially deposited on the surface of the substrate. Over the Si02 layers 21 grow polycrystalline regions 42; a mono-crystalline- layer 41 grows over the remainder of the substrate. Fig. 4 shows what is done next: Another Si02 film 22 is deposited onto the surface of the epitaxial layer, and then is partially etched away to expose, inter alia, the semiconductor surface di — 1384 — rectly over the SÍO2 layers 21. Thereafter, a P-type impurity is thermally diffused into the device, creating P-type circuit elements 51a and 51b as well as P-type isolating layers 52 and isolating PN junctions 53. Thus, the formerly N~ type polycrystalline regions 42 (Fig. 3) have been changed to P-type regions 52 (Fig. 4). Since impurities diffuse through polycrystalline regions much more rapidly than through monocrystalline regions, P-type isolating regions 52 may be grown through the N-type epitaxial layer down to the P-type substrate 1 without corresponding penetration to the substrate of circuit elements 51a and 51b. The Cited Patents Iwata et al. (Iwata) 3,475,661 Oct. 28, 1969 Manasevlt et al. (Manasevlt) 3,393,088 July 16, 1968 Doo 3,386,865 June 4, 1968 The application that matured into the Iwata patent was filed in the United States on February 6, 1967, which was after appellant’s Japanese priority date. Iwata’s invention provides electrical isolation of semiconductor elements by including in otherwise monocrystalline epitaxial layers polycrystalline regions into which impurities are diffused to produce PN junctions between the polycrystalline and monocrystalline portions. The Iwata specification and drawings explain the invention more fully (emphasis ours): In FIGURE 1, reference numeral 10 indicates generally a P-type single crystal silicon substrate having a plurality of continuous or discontinuous grooves 11 formed on one face thereof. The grooves 11 act as sites for growing subsequently applied polycrystalline layers. An N-type silicon epitaxial layer 12 is then deposited over the grooved surface by means of vapor deposition. The grooves 11 cause the N-type silicon to be deposited as polycrystalline regions 13 which grow into a generally wedge shape. The remainder of the layer 12 is a single crystal layer of N-type silicon. Epitaxial growth processes are well known in the art and provide an extension of the original crystalline structure of the substrate, with the atoms of the epitaxial layer being aligned as a continuation of the original crystalline structure. In a typical epitaxial growth process, the substrate is heated in a reaction chamber and a gas stream containing vapors of a silicon halide such as silicon tetrachloride doped with a small amount of phosphorous trichloride is passed over the heated substrate in the chamber under vacuum conditions. A reaction takes place at the surfaces, and a film or layer of silicon grows in monocrystalline form on the surface of the substrate. The impurity material also deposits in elemental form along with the silicon on the substrate. Following the deposition of the epitaxial layer 12, the substrate is heated to diffuse the P-type impurity from the substrate 10 into the epitaxial layer 12. The acceptor impurity contained in the substrate 10 diffuses into the polycrystalline areas 18 more rapidly than in the single crystal area so that a diffused area-14 substantially surrounding the wedge-shaped polycrystalline area 13 is produced, the diffused area 14 providing PN junctions between the single crystal area 12 and the substrate 10. The PN junction is substantially uniform in thickness, both at the region where it is parallel — 1385 — to the substrate 10 and the region overlying the wedge-shaped polycrystalline areas 13. Sites for the production of polycrystalline areas as part of an epitaxial growth process can also be provided by depositing a layer of silica on the substrate instead of providing grooves. The silica particles provide discontinuities which behave in substantially the same manner as the grooves 11 shown in the figures. Having produced his polycrystalline regions 13 and having diffused them to produce PN junctions, Iwata describes how he can produce semiconductor devices as follows, referring to Fig. 5 of his drawings: FIGURE 5 illustrates the production of an integral circuit semiconductor device using the process of the present invention. In the manufacture of the integral circuit of FIGURE 5, the steps of FIGURES 1 through 3 are repeated after which the upper surface of the device is planed or otherwise cut to provide a surface 17 in which portions of the polycrystalline area 13 are exposed. Alternatively, the epitaxial layer 12 can be grown originally so that the upper ends of the polycrystalline area 13 extend up to the surface of the single crystal layer 12, i. e., the depth of deposition of the epitaxial layer 12 can be controlled so that it does not exceed the height of the polycrystalline area 13. In the device of FIGURE 5, the single crystal epitaxial layers 12 are electrically separated from each other by PN junctions 14 so that the individual areas 12 can each provide circuit elements such as transistors, diodes, capacitors or resistances. The improved elements of the present invention can also be made by other modified techniques, e. g., starting with a substrate of P-type silicon, an epitaxial layer of P-type silicon can be deposited on the substrate, with the formation of polycrystalline areas as previously described. Then, a donor impurity can be diffused through the substrate and through the polycrystalline areas to form individual epitaxial areas which are separated from the polycrystalline areas by PN junctions. As a further modified form of the invention, an intrinsic silicon substrate can be provided with an epitaxial layer of P-type silicon with intermediate polycrystalline areas. Then, the donor impurity can be diffused through the epitaxial layer to form diffused areas which provide PN junctions between the polycrystalline areas and the P-type epitaxial layer. As will be explained later, the examiner and the board used, in the rejection of appellant’s claims, claims 1-5 of Iwata, which read as follows: 1. A semiconductor device comprising a substrate of one conductivity type, means on said substrate providing discontinuities in the surface thereof, a layer of the opposite conductivity type formed on said substrate and constituting an extension of the original crystalline structure of said substrate, said layer including spaced polycrystalline portions over said discontinuities, and a diffused region along said polycrystalline portions providing PN junctions between said polycrystalline portions and said layer. 2. The device of claim 1 in which said diffused region contains the same impurity as exists in said substrate. 3. The device of claim 1 in which said polycrystalline portions are surrounded by said diffused region. 4. The device of claim 1 in which said polycrystalline portions extend — 1386 — upwardly to and are exposed at the surface of said layer. 5. A semiconductor device as claimed in claim 1 wherein said discontinuities are provided by a layer of silica formed on said substrate. Iwata’s claim 10, also referred to by the examiner, reads: 10. A semiconductor device as claimed in claim 1 wherein said discontinuities are provided by grooves formed on said substrate. Manasevit was cited by the examiner to show the use of an insulating sapphire substrate upon which monocrystalline silicon may be grown, as used by appellant in one embodiment. Doo discloses methods for isolating regions on planar semiconductor devices by surrounding the regions by isolation channels of encapsulating materials including silicon dioxide which extend from the surfaces of the isolated regions to the substrate. Prosecution History and Rejection In response to the examiner’s first rejection of claims as obvious in view of Iwata, Manasevit, and Doo, appellant attempted to dispose of the principal reference, Iwata, by claiming the right of priority of his corresponding Japanese application, filed in Japan August 31, 1966, prior to Iwata’s U. S. filing date. The examiner followed with a final rejection, rejecting claims 10, 11, 16 and 18 “under 35 U.S.C. 102 as anticipated by the claims of Iwata” (emphasis in original), and rejecting claims 13, 14, 15, 17, and 19 “under 35 U.S.C. 103 as unpatentable over the claims of Iwata” (emphasis in original), either alone or taken with Doo. The final rejection concluded (emphasis ours): Since the claimed invention of this application is regarded to be substantially the same as the claimed invention of the Iwata et al patent, the latter may be overcome only through interference proceedings. See MPEP 1101.02(a). Applicant cannot remove the Iwata et al patent as reference merely by claiming foreign priority and filing a certified copy as well as a sworn translation of the corresponding Japanese application. Priority as to the common claimed subject matter must be determined in an interference proceeding, since it appears that Iwata et al may be entitled to a priority date prior to that of applicant as to such common claimed subject matter. Therefore, applicant is given THIRTY (30) DAYS from the date of this letter to copy claims 1 and 5 of Iwata et al as well as any other claims of the patent which he believes find support in his application. See MPEP 1101.-02(b), Rules 204 and 205. Failure to make said claims will be considered a disclaimer of the subject matter involved. Appellant refused to copy the claims, contending that he could not make the limitation in Iwata’s claim 1 calling for “means on said substrate providing discontinuities in the surface thereof” (emphasis ours). Since Iwata disclosed the formation of these discontinuities by grooves 11 made in the substrate, appellant, who discloses no grooves, argued he could not make claim 1. Claims 2-5 are all dependent. Furthermore, appellant noted that Iwata speaks of discontinuit ies and polycrystalline layers over the discontinuities in the plural and contended that his own claims called for only one polycrystalline semiconductor layer surrounding the monocrystalline region completely, a feature not described by the claims of Iwata. The examiner did not accept appellant’s arguments and continued his final rejection, adding Iwata’s claims 2-4 to those whose subject matter he held to be disclaimed by appellant for refusal to copy. In his Answer the examiner ex-, plained his position more fully: 1) Applicant has disclaimed the invention by refusing to copy claims 1 and 5 of the Iwata et al patent. Claim 1 of Iwata et al is broad and generic to claims 5 and 10. Claims in a patent are construed in their broad — 1387 — est context. Applicant has argued that he cannot make claim 1 of Iwata et al. That argument is based upon erroneous interpretations of the claim. Claim 1 of Iwata et al is not limited to grooves in the surface of the substrate. The claim language is in the means plus function clause, “means on said substrate providing discontinuities in the surface thereof.” Means plus function clauses are interpreted in light of the disclosure. Also note claim 5. So what the claim says is that in the surface of the substrate there are provided discontinuities, and that includes a discontinuity in the surface caused by a projecting silica layer as well as a groove. • Even by applicant’s own definition of discontinuity “1. want of continuity or cohesion” the surface of Iwata et al is continuous be it by a groove or a silica protrusion. * * * And further with respect to applicant’s own U. S. disclosure, who is to say that a thermally grown Si02 layer is on or in the surface part of the silicon surface since such a process consumes the surface. Claim 5 of Iwata et al does not broaden the claim but merely states that the means on the substrate providing the discontinuities in the surface is a layer of silica on the substrate. Since, Iwata’s claim is generic Ex parte Embree and Doyle, 151 P.Q. 354 [(Bd.App.1965)] is not applicable. Applicant by not copying claims have [sic] disclaimed the subject matter of claim 1-5 of Iwata et al and is es-topped from claiming Iwata et al’s invention as his own. Nor is applicant permitted to attain claims that do not patentably distinguish from that which is disclaimed. [Last two emphases ours.] The examiner concluded: Applicant is estopped from claiming Iwata et al’s invention as his own having disclaimed the subject matter, and the claims are unpatentable over Iwata et al as prior art * * *. The board sustained all of the rejections, finding that appellant could make claims 1-5 of Iwata. It said: We are convinced that Iwata et al and appellant are claiming the same invention. The examiner has used only the claims of Iwata et al as a basis for rejection. In our opinion all of the subject matter in Iwata et al necessary to support the claims is available as reference material. * * * Appellant has disclaimed the subject matter of Iwata et al by failing to contest priority as to the claimed subject matter. Having determined that Iwata et al is a valid reference against the claims, we sustain the [examiner’s] rejections H« * * OPINION Claim 12 Since claim 12 is admittedly not entitled to appellant’s Japanese filing date, Iwata is “prior art” to this claim within the meaning of 35 U.S.C. § 103, by virtue of 35 U.S.C. § 102(e). We agree with the examiner and the board that claim 12 would have been obvious to a person of ordinary skill in the art familiar with Iwata and Manasevit. We agree with appellant that Manasevit’s inventive contribution to the art lies in the description of the crystal planes along which the insulating sapphire support substrate should be cut so that monocrystalline silicon may be epitaxially deposited thereon, but this is not the measure of Manasevit’s disclosure as evidence of what a person of ordinary skill in the art would have known when appellant made his invention. Manasevit shows it was known to grow monocrystalline semiconductor layers on insulating substrates. Insulating substrates, we are told, have the advantages of eliminating undesirable stray electrical effects encountered in devices fabricated with support substrates of semiconductor — 1388 — material and acting as heat sinks during operation. By teaching that the substrate must be smooth and' free of scratches and dust in order to insure uniform crystallographic results, i. e., uniformly monocrystalline epitaxial layers, Manasevit suggests that imperfections in the substrate surface give rise to imperfections in the epitaxial layers grown thereon, i. e., polycrystalline growth. In light of the disclosure in Manasevit we find that it would have been obvious to a person of ordinary skill in the art to employ insulating substrates to his advantage in fabricating semiconductor devices, disclosed by Iwata, having mono-crystalline circuit elements isolated by PN junctions formed by doped polycrystalline isolating regions grown over discontinuities in the substrate. The Remaining Claims (10, 11, 13-19) — Disclaimer The board sustained the examiner’s holding, underlying his specific rejections stated to be under 35 U.S.C. §§ 102 and 103, that appellant has “disclaimed the subject matter of claims 1-5 of Iwata et al.” Both the examiner and the board referred to this holding as “a rejection.” We do not consider the disclaimer of Iwata claims to be in itself a rejection of appellant’s claims; it is, rather, the principal basis upon which appellant’s claims have been rejected, either as “anticipated” by Iwata’s invention or as obvious in view of Iwata’s invention alone or taken with Doo. The board sustained the § 102 and § 103 rejections as stated by the examiner, and the only possible basis on which it could have done so is on the basis that Iwata’s invention, as defined in his claims 1-5, can be used as the conceded prior invention of another in this country under § 102(g) and thus as prior art under § 103, a prior invention by another in this country of the subject matter claimed being what is meant by “anticipation.” This is for the reason that, except as to claim 12, the Iwata patent, either as patent or printed publication, is not a prior art reference because of the Japanese filing date to which the board has held appellant entitled. It is because of this difference in the way we analyze the basis of the rejection that we cannot fully approve of all of the reasoning stated below, although we do agree fundamentally with the rejections of claims 10, 11, and 13-19 on the statutory grounds stated. This brings us to a consideration of the propriety of using the Iwata invention, as shown by his patent, as prior invention or prior art to appellant. In implementation of 35 U.S.C. § 135, which provides, inter alia, for interferences and the determination of priority of invention therein, the PTO has promulgated Rules 201 and 203 (37 CFR 1.201 and 1.203): 201. * * * (b) An interference will be declared between pending applications for patent, or for reissue, of different parties when such applications contain claims for substantially the same invention, which are allowable in the application of each party, and interferences will also be declared between pending applications for patent, or for reissue, and unexpired original or reissued patents, of different parties, when such applications and patents contain claims for substantially the same invention which are allowable in all of the applications involved, in accordance with the provisions of the regulations in this part. 203. * * * (b) When the claims of two or more applications differ in phraseology, but relate to substantially the same patentable subject matter, the examiner shall, if it has been determined that an interference should be declared, suggest to the parties such claims as are necessary to cover the common invention in the same language. The parties to whom the claims are suggested will be required to make those claims (i. e., present the suggested claims in their applications by amendment) within a specified time, not less than 30 days, in order that an interference — 1389 — may be declared. The failure or refusal of any applicant to make any claim suggested within the time specified, shall be taken without further action as a disclaimer of the invention covered by that claim unless the time be extended. We find that the examiner properly found, in accordance with these rules, that appellant and the Iwata patent claim substantially the same invention, and that Iwata claims 1 — 5 are suitable interference counts, being supported by appellant’s specification. It is apparent that appellant and Iwata have disclosed a common, single invention, although Iwata’s total inventive contribution is broader than that of appellant. The one invention made by both inventors relates to semiconductor devices having electrical elements isolated by PN junctions formed in polycrystalline areas grown epitaxially over layers of silica (SÍO2) deposited on the surface of the substrate of the device. This is clearly what Iwata regarded as part of his invention and is the heart of what appellant claims. Although appellant’s brief does not organize the issues exactly as we have, it appears that appellant considers his invention to differ from Iwata’s in one material respect, namely, that Iwata’s grooves 11, on which isolating polycrystalline regions are grown, allegedly do not completely surround the circuit elements of Iwata’s device; whereas appellant considers completely surrounding the circuit elements to be an essential part of his invention. Appellant bases this argument on Fig. 1 of Iwata, which shows parallel grooves 11 extending from one side of the substrate to the other. This is a distinction without a difference. Fig. 1 represents only one embodiment of Iwata’s invention. Iwata’s specification considers the invention to lie in producing “Isolation between the various sections of the semiconductor device * * * by providing * * * PN junctions between the polycrystalline portions and the single crystal portions.” Iwata’s claims are directed to this very subject matter. We see no materialdifference between an invention in which polycrystalline regions provide PN junctions isolating various sections of the device and one in which the polycrystalline isolating layers surround the various sections of the device. The result achieved is the same, and the means employed are also the same. In this case the PTO, having insisted that appellant should have copied Iwata’s claims, must show, in support of that contention, that appellant had support for the claims in his application. We enunciated the conditions precedent to copying claims in Dreyfus v. Sternau, 357 F.2d 411, 415, 53 CCPA 1050, 1054 (1966): First, one copying a claim from a patent for the purpose of instituting interference proceedings must show that his application clearly supports the count. Jepson v. Coleman, 314 F.2d 533, 50 CCPA 1051 [(1963)]. There must be no doubt that an application discloses each and every material limitation of the claims and all doubts must be resolved against the copier. The PTO has shown that appellant had the necessary support. Appellant contends that his application does not support the limitation in Iwata claim 1, which is carried into dependent claims 2-5, calling for “means on said substrate providing discontinuities in the surface thereof” (emphasis ours), for the reason that his SÍO2 layers 21 (see Fig. 3 of appellant’s application, supra) provide discontinuities on and not in the substrate. We may use the Iwata specification as a dictionary to determine what this limitation means. In re Vogel, 422 F.2d 438, 57 CCPA 920 (1970). Iwata explains that the grooves 11, which unquestionably extend from the original surface of the substrate into the body of the substrate, “act as sites for growing subsequently applied polycrystalline layers.” Appellant does not disclose grooves. However, Iwata then states that sites for epitaxial growth may be provided (emphasis ours), * * * by depositing a layer of silica [SÍO2] on the substrate instead of pro — 1390 — viding grooves. The silica particles provide discontinuities which behave in substantially the same manner as the grooves 11 shown in the figures. From this we conclude that the SÍO2 layers disclosed by appellant are among the “means on said substrate providing discontinuities in the surface thereof” defined by Iwata claim 1 and that appellant’s disclosure will support both claim 1 and claim 5, which is directed specifically to the SÍO2 layers providing sites for polycrystalline growth. Appellant has not disputed that his application supports the remaining limitations of claim 1. And appellant does not deny that the limitations added by claims 2-4 also find support in his specification. Since we agree with the board that appellant claims essentially the same invention as Iwata, and that he could have copied the claims suggested by the examiner but has refused to do so, we see no reason why appellant should not suffer the same consequences that would have befallen him had he entered the interference and either conceded priority of invention in the subject matter of Iwata claims 1-5 or lost priority on evidence of prior inventorship by another in this country of the subject matter of the claims. When a party who has contested and lost priority with respect to a count in an interference presents claims ex parte that define subject matter obvious in view of the subject matter of the lost count, as shown by prior art references or by reference to the ordinary skill of the art, rejection of those claims under § 103 may be proper if the subject matter of the count falls within any of the paragraphs of § 102. In re Risse, 378 F.2d 948, 54 CCPA 1495 (1967). The same result obtains where the party concedes priority of invention of a count. As we pointed out in Risse, such a rejection is based not on interference estoppel, but on a determination that the subject matter of the count is the prior invention of another under § 102(g), or falls within another paragraph of § 102, and may be used as “prior art” in combination with other references under § 103. In Risse we said (emphasis in original): The distinction which should be borne in mind is that, with regard to interference estoppel, the losing party is only estopped to obtain claims which read directly on disclosures of subject matter clearly common to both the winning party’s application and that of the losing party; but that, with regard to prior art (including prior invention), the losing party cannot obtain claims to subject matter which is either barred under 35 U.S.C. § 102(g), or rendered obvious under 35 U.S.C. § 103, by the invention defined in the interference counts. [378 F.2d at 957, 54 CCPA at 1506.] We recognize the continuing vitality of the doctrine of interference estoppel described in Risse in appropriate factual settings. The circumstances in this case, however, require that we follow by analogy the law applied to situations in which priority of invention is actually determined, whether by concession or contest. Appellant was told by the examiner, correctly we have found, that he and Iwata claimed the same invention and, again correctly, that appellant should copy Iwata claims 1 and 5, and any others he might be able, to make, under penalty of disclaimer. Appellant was not misled by the examiner’s requirement, which is consistent with the rule that an applicant claiming the same subject matter as another applicant or a patentee may not receive those claims unless the PTO, pursuant to 35 U.S.C. § 135, administratively determines who was the prior inventor of the subject matter. That appellant might have been the senior party in an interference with Iwata, and thus not be subject to interference estoppel if the interference were dissolved for appellant’s lack of a right to make the count,2 is immaterial. Appellant cannot rely on the priority of his — 1391 — Japanese filing date at this stage to overcome Iwata since, by refusing to enter into an interference, appellant has deprived Iwata of an opportunity to prove priority of invention vis-a-vis appellant.3 Iwata has his patent and another patent for the same invention cannot be issued unless priority is determined in appellant’s favor. We hold that appellant’s refusal to copy Iwata claims 1 — 5, which he could make, resulted in a concession (termed “disclaimer” in PTO Rule 203(b)) that the subject matter of those claims is the prior invention of another in this country under § 102(g) and thus prior art to appellant under § 103. In determining that the subject matter of Iwata claims 1-5 is effectively prior art to appellant, we are not agreeing with the board that “all of the subject matter in Iwata et al necessary to support the claims is available as reference material.” (Emphasis ours.) Appellant has made no concession and is subject to no disclaimer with respect to the disclosure of Iwata. The disclosure is available only to determine what invention the claims define and hence what invention has been disclaimed so as to be available as prior art. Appellant cites cases which he asserts hold that subject matter disclaimed by failure to copy suggested claims cannot be used as prior art under § 103, namely, Ethyl Gasoline Corp. v. Coe, 78 U.S.App.D.C. 233, 139 F.2d 372 (1943) and Ex parte Embree and Doyle, 151 USPQ 354 (Bd.App.1965). The board in Embree cited Lyon v. Boh, 10 F.2d 30 (2d Cir. 1926). In Ethyl Gasoline the applicant, Bartholomew, refused to copy a claim suggested by the examiner because, he contended, his application would not support the suggested claim. The examiner had warned Bartholomew that failure to copy would result in disclaimer under Rule 96, the predecessor of the present Rule 203(b). In response to the Patent Office’s defense of its rejection of Bartholomew’s claims that Bartholomew’s failure to copy made the subject matter of the suggested claim prior art to him, the court stated: Assuming the validity of Rule 96, its effect is to establish, under certain circumstances, an estoppel against the applicant who declines to present a suggested claim. Just what the nature and extent of that estoppel may be is not necessary to decide. It is enough to say that we cannot support the theory of the Patent Office that the disclosures of the suggested claim constitute prior art against the applicant. The extent of estoppel will depend, in the particular case, upon how the suggested claim is drawn and for what reason it is refused by the applicant. Under some circumstances the result may be similar to that which would obtain if the teachings of the prior art had been sufficient to bar a patent. But only in this limited sense is the analogy permissible. The confusion, between an estoppel and the condition of the prior art,6 has been unfortunate and misleading. [Emphasis ours; footnotes 4 and 5 omitted.] Footnote 6 cited In re Williams, 62 F.2d 86, 20 CCPA 738 (1932). Since the rejection had been made solely on the basis of Bartholomew’s refusal to make the suggested claim, the court made no finding on whether Bartholomew’s application had support for the claim. We do not conclude from the above, as appellant desires, that disclaimed subject matter may never be used as prior art. In Williams appellants were a party in an interference. After the interference was declared, appellants cancelled the claims in their application corresponding — 1392 — to the interference counts and filed a disclaimer stating that the invention of the counts was broader than their joint invention and was the sole invention of appellant McCabe. The rejection of the remaining claims using the interference counts as prior art was sustained by the court, since * * * appellants having admitted that they are not entitled to the interference counts, they also are not entitled to any subject matter failing to define [patentable] invention there-over, and the disclaimed interference issue is available with the same effect as a prior art reference disclosing such subject-matter. It is implicit that the Williams application supported the interference counts. We see no inconsistency between Williams and Ethyl Gasoline. The citation of Williams in Ethyl Gasoline as an illustration of the distinction in disclaimer situations between estoppel and “the condition of the prior art” shows that the court recognized that a disclaimer by failure to copy suggested claims can act as an admission that the disclaimed subject matter is prior art, as the circumstances dictate. It was not necessary for the court in Ethyl Gasoline to decide the effect of Bartholomew’s refusal to copy because the record did not show whether Bartholomew’s refusal to copy was justified. This is confirmed by the court’s remand of the case for a trial “on the merits.”4 Thus, the court in Ethyl Gasoline was leaving open for decision on remand the question of what the applicant’s refusal to copy the claims signified. In Embree the applicants refused to copy a suggested claim to a species apparently within a genus already claimed in their application. The Board of Appeals held, on the authority of Ethyl Gasoline, that the subject matter of the suggested claim could not be used as pri- or art. The board did not hold that the application supported the suggested claim, nor can we reach such a conclusion from reading the board’s opinion. In Lyon v. Boh, supra, cited by the board as additional authority, the court found that an applicant’s failure to copy claims, which were conclusively determined to be for subject matter wholly different from that claimed by the applicant, resulted in a disclaimer only of the particular species defined by the suggested claims. Neither Embree nor Lyon is apposite to this case, since in neither was it found that the applicants could have copied the suggested claims. This finding, we have shown supra, is critical in determining the consequences of disclaimer for failure to copy suggested claims. On the merits of the rejections before us, we see either no differences or no unobvious differences between the subject matter of Iwata claims 1-5 and appellant’s claims 10, 11, and 13 — 19. We have explained above why we think Iwata claims 1-5 describe monocrystalline circuit elements completely surrounded by polycrystalline isolating layers. The Doo reference is further cumulative evidence that persons of ordinary skill in the art know that semiconductor regions intended to be isolated must be completely surrounded with the means providing isolation. Appellant’s argument that Iwata does not claim a plurality of monocrystalline regions isolated by polycrystalline layers is without merit in light of Fig. 5 of Iwata, which shows the devices claimed by Iwata to contain several monocrystalline regions. Appellant admits that the “insulator layer” in claims 11 and 14 refers to his SÍO2 layer 21, which is one of the means providing sites for the growth of polycrystalline layers claimed in Iwata claims 1 and 5. — 1393 — Claim 15 recites “silicon oxide” as the insulator of claim 14, which appellant alleges is SiO, not the silica (which is SÍO2) claimed in Iwata. Appellant’s specification makes no mention of SiO, so we see no reason why claim 15 does not refer to silica, which is a silicon oxide, as the insulator. Conclusion The decision of the board affirming the rejections of claims 10-19 is affirmed. Affirmed. APPENDIX The Appealed Claims 10. A semiconductor device, comprising a support substrate having a main surface, monoerystalline semiconductor layers of a first conductivity type provided on said main surface, and a semiconductor layer of a second conductivity type opposite said first conductivity type which is provided on said main surface to integrally connect to said monoerystalline semiconductor layers and which contains polycrystalline semiconductor layers, said monoerystalline layers being directly connected with and surrounded by said semiconductor layer of the second conductivity type. 11. A semiconductor device as set forth in Claim 10, wherein said support substrate is formed of the same kind of semiconductor of said second conductivity type as said monoerystalline semiconductor, and an insulator layer is interposed between said polycrystalline semiconductor layer and said substrate. 12. A semiconductor device as set forth in Claim 11, wherein said support substrate is formed of an insulating material. 13. A semiconductor device, comprising a support substrate having a main surface, a semiconductor layer of a first conductivity type provided on said main surface and which includes a polycrystalline semiconductor layer, a plurality of monoerystalline semiconductor layers of a second conductivity type different from said first conductivity type which are disposed on said main surface and are completely surrounded by and integrally connected to said semiconductor layer of the first conductivity type and electrically isolated from each other by the latter semiconductor layer, and circuit elements defined respectively in said plurality of semiconductor layers. 14. A semiconductor device as set forth in Claim 13, wherein said support substrate is formed of a monoerystalline semiconductor of said first conductivity type, and an insulator layer is interposed between said polycrystalline semiconductor layer and said support substrate. 15. A semiconductor device as set forth in Claim 14, wherein each of said semiconductors is silicon and said insulator is silicon oxide. 16. A semiconductor substrate for making an integrated circuit, comprising: a monoerystalline semiconductor body of a first conductivity type; a plurality of monoerystalline regions of a second conductivity type opposite to said first conductivity type, said mono-crystalline regions being epitaxially grown on a main surface of said mono-crystalline semiconductor body; a polycrystalline semiconductor layer of said first conductivity type completely surrounding and interposed among said plurality of monoerystalline regions and isolating the monoerystalline regions from each other; and an insulating layer interposed between said polycrystalline semiconductor layer and said monoerystalline semiconductor body. 17. A semiconductor device comprising: a monoerystalline semiconductor substrate of a first conductivity type; a plurality of monoerystalline regions of a second conductivity type opposite to said first conductivity type, said mono-crystalline regions being epitaxially grown on a main surface of said mono1394 crystalline semiconductor substrate, a plurality of circuit elements being formed in said plurality of monocrystalline regions; an isolation region completely surrounding and interposed among said plurality of monocrystalline regions for electrically isolating said monocrystalline regions from each other, said isolation region including polycrystalline semiconductor materia] and defining rectifying barriers with said plurality of monocrystalline regions; and an insulating layer interposed between said monocrystalline semiconductor substrate and said isolation region. 18. A semiconductor substrate for manufacturing an integrated circuit, comprising: a monocrystalline support member having a plane major surface; a plurality of monocrystalline semiconductor regions provided on said plane major surface, spaced from each other and adapted to form a circuit element in each thereof; and an isolation region completely surrounding and interposed among said plurality of monocrystalline semiconductor regions and including polycrystalline semiconductor layer of a conductivity type opposite to that of said monocrystalline semiconductor regions. 19. A semiconductor device comprising a monocrystalline semiconductor substrate having a major surface of a first conductivity type, a plurality of monocrystalline semiconductor layers of a second conductivity type epitaxially grown on said major surface of said substrate and spaced from each other, a polycrystalline semiconductor layer completely surrounding and in direct contact with said plurality of monocrystalline semiconductor layers, said polycrystalline semiconductor layer including an impurity determining said first conductivity type, an insulating layer provided on said major surface of said substrate and interposed between said polycrystalline semiconductor layer and said substrate, and a circuit element formed in each of said monocrystalline semiconductor layers. ' Footnotes [1] A division of application No. 662,646, filed August 23, 1967. Appellant claimed the right of foreign priority based on an application filed in Japan August 31, 1966, which the board granted to all of the claims except claim 12, the denial of priority to which appellant does not contest, [2] Plumat v. Dunipace, 464 F.2d 1402, 59 CCPA 1295 (1972). [3] From Iwata’s patent it appears that Iwata may be able to claim a Japanese filing date prior to appellant’s corresponding date. By so doing Iwata might win the interference. Iwata might also be able to show a prior reduction to practice of his invention in this country, for instance, by proving that his invention was introduced into the United States before appellant’s Japanese filing date. [4] The court indicated that at “oral argument the Commissioner conceded that if the interpretation contended for in his brief were pressed to its logical limits, then Rule 96 and the practice under it would be arbitrary and capricious.” We agree that it would be unfair to applicants if examiners had free rein to create “prior art” by suggesting claims whether the applicants had support for the claims or not. The abuse which concerned the court would not exist if disclaimed subject matter were considered prior art only if suggested claims embodying that matter were supported by the applications.